Various techniques have been developed for fabricating semiconductor devices having small geometry features, such as on the order of 0.25 micron and below. Logic devices developed using small geometry fabrication processes often provide for low threshold voltages and reduced power consumption.
Increasing the speed at which a digital logic device transitions between logic states, commonly referred to as switching speed, has long been a primary motivation behind many advancements in the semiconductor arts. Increasing the switching speed of a logic device, however, results in a proportional increase of the power consumed by the device. The power consumed by a digital logic device while switching between logic states is commonly referred to as dynamic power consumption. As the demand for faster logic devices continues to increase, reducing the dynamic power consumption of logic devices continues to be of paramount importance in many high speed, low power applications.
Interestingly, dynamic power consumption is of less importance in applications where high switching speeds are not required or desired. In digital circuits that have relatively low switching frequencies, such as those typically employed in implantable medical devices, static power consumption becomes a predominate factor that, if left unaddressed, typically results in a dramatic increase in the overall level of power consumption. Static power consumption is understood in the art as power consumed by a device during periods in which no switching occurs. In some applications, static power consumption predominates over dynamic power consumption in the average power consumption equation.
The past and present focus by the semiconductor industry on reducing dynamic power consumption in high-speed digital logic devices has overshadowed the problems of increased static power consumption in digital devices and circuits designed to operate at low switching frequencies.
There is a need in the semiconductor manufacturing industry for an approach to reducing power consumption in digital logic devices and circuits intended for use in low switching frequency applications, such as implantable medical device applications. There is a further need for an approach that addresses problems associated with increased static power consumption in such digital logic devices and circuits. The present invention fulfills these and other needs.